`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:00:26 03/27/2014 
// Design Name: 
// Module Name:    music 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module music(speaker, gain, 
shutdown, clk, switch1, switch2, switch3, switch4);   

	input clk, switch1, switch2, switch3, switch4;   
	output speaker, gain, shutdown;  
	reg shutdown = 1;
	reg gain = 1;
	wire  dclk, sound1, sound2, sound3, sound4;
	wire [2:0] sig, sigO;
	
	assign sig = {switch2,switch3,switch4};
	CLK_div CLK(dclk, clk);
	Interface inter(sigO, sig, dclk);
	
	//Debouncer de(ds1, switch1, clk);
	One  one(sound1, dclk);
	Three three(sound2, dclk);
	Song song(sound3, dclk, switch3);
	Tone tone(sound4, dclk, switch4, sigO);
	
	assign speaker = (switch4==1'b1)? sound1 :
							(switch3==1'b1)? sound2 :
							(switch2==1'b1)? sound3 :
							(switch1==1'b1)? sound4 : 1'b0;
	
endmodule   
